Efficient Test Data Compression and Fault Analysis in VLSI Circuits - Bog af Sivaganesan Subramaniam - Paperback

Efficient Test Data Compression and Fault Analysis in VLSI Circuits - Sivaganesan Subramaniam

In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory...